NNSE: Nostrum Network-on-Chip Simulation Environment
نویسندگان
چکیده
A main challenge for Network-on-Chip (NoC) design is to select a network architecture that suits a particular application. NNSE enables to analyze the performance impact of NoC configuration parameters. It allows one to (1) configure a network with respect to topology, flow control and routing algorithm etc.; (2) configure various regular and application specific traffic patterns; (3) evaluate the network with the traffic patterns in terms of latency and throughput.
منابع مشابه
An Empirical Power Model of the Links and the Deflective Routing Switch in Nostrum
An empirical power model of the switch-to-switch links and the hot potato switch in Nostrum has been developed based on an analytical analysis and experiments with Synopsys Power Compiler. The model takes into account all possible variations of bit patterns of packets travelling through the network. It has been validated against Power Compiler simulations and is accurate within a few percent. T...
متن کاملImplementation of a JPEG Encoder on Nostrum Network-on-Chip
The techniques of Network-on-Chip become more and more mature and useful recently years. With this trend, DSP applications such as audio/video, encoding/decoding, image processing can usually be modeled as data-flow process networks (PNs). A JPEG encoder can be a very useful application on Network-on-Chip. In this project, we use a JPEG encoding program at the Application Layer as our applicati...
متن کاملEvaluating NoC communication backbones with simulation
This paper describes a Network on Chip simulator that was developed to evaluate our NoC architecture Nostrum. It is shown how SystemC’s features for communication refinement is used to make a highly flexible simulator. The simulator is reconfigurable so that it is possible to try different NoC platforms and different mappings of workloads. In addition to the modeling of our Nostrum architecture...
متن کاملPANACEA - A case study on the PANACEA NoC - a Nostrum Network on Chip prototype
PANACEA is a prototype chip based on the Nostrum Network on Chip concept. It has been developed in a semester thesis at the Integrated Systems Laboratory (IIS) at the Swiss Federal Institute of Technology Zürich (ETHZ). The discussion and results in this paper are based on the thesis. The PANACEA NoC is a 4× 4 network mesh Switches with resources that are used for packet transmission and statis...
متن کاملGeneralization of Slot Table Size for Virtual Circuits on Nostrum Networks on Chip Master of Science Thesis
Since the late 1990's, the trend of integrated circuit design has been integrating several system components or IP blocks, such as processors and memories, on one chip. This is referred to the concept of System on Chip (SoC). However, with the increase of system scales in SoC systems, some problems such as inter-connection communication, scalability, system throughput and response time of the s...
متن کامل